Integrated circuit burn-in methods and apparatus

ABSTRACT

Improved methods for performing burn-in of electronic components, such as integrated circuits (ICs) with on-board thermal sense circuits, are used to obtain a higher bin split. According to one embodiment, a thermal set-point is loaded into each IC. While the ICs are maintained at a constant elevated temperature, the burn-in system checks each IC to determine whether the set-point has been exceeded. If so, it characterizes the IC by that set-point; if not, it decrements the set-point and checks again. The method continues until all ICs have been characterized to a specific set-point. As a result of the method, a junction temperature is obtained for each IC. In addition, a real-time estimate of the burn-in time for each IC is obtained, so that burn-in time can be adjusted to maximize burn-in throughput. Apparatus for implementing improved IC burn-in is also described.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates generally to the field ofelectronics and, more particularly, to improved methods and apparatusfor performing burn-in testing on electronic components such asintegrated circuits.

BACKGROUND OF THE INVENTION

[0002] In the field of electronic systems there is an incessantcompetitive pressure among manufacturers to drive the performance oftheir equipment up while driving down production costs. This isparticularly true regarding the testing of integrated circuits(hereinafter “ICs”). ICs must generally be tested before they areincorporated into an electronic assembly in order to verify that eachelement on the IC functions properly.

[0003] It is well known to perform accelerated life testing on ICs toensure that the ICs do not prematurely fail when they have beenincorporated into higher levels of electronic packaging, such as acomputer systems, (e.g., desktop, laptop, hand-held, server, etc.),wireless communications devices (e.g., cellular phones, cordless phones,pagers, etc.), computer-related peripherals (e.g., printers, scanners,monitors, etc.), entertainment devices (e.g., televisions, radios,stereos, tape and compact disc players, video cassette recorders, MP3(Motion Picture Experts Group, Audio Layer 3) players, etc.), and thelike.

[0004] A goal of burn-in is to provide infant-mortality screening of ICsfor reliability defects. By operating the ICs at increased voltageand/or temperature levels, while stimulating as many transistors on theICs as possible, ICs that might fail prematurely are identified earlyand pulled out prior to shipment to customers. It is desirable to keepburn-in time (BITM) to a minimum to reduce production costs.

[0005] As high performance ICs are packed with increasing numbers oftransistors numbering in the millions, the transistor channel lengthL_(e) has been made increasingly shorter to improve performance.Generally, the shorter the channel length L_(e) the higher the leakagecurrent I_(SB). As the leakage current I_(SB) increases, so does thecorresponding power requirement, and the attendant heat dissipation.Thus, testing large quantities of ICs can require substantialconsumption of electrical power resources, even as such resources becomeincreasingly scarce and costly.

[0006] It is desirable to thoroughly test ICs undergoing burn-in testingwhile at the same time minimizing the cost, time, and complexity of suchtesting.

[0007] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a significant need inthe art for improved IC burn-in methods and apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 illustrates a block diagram of a system to performcomponent burn-in testing and binning, in accordance with one embodimentof the invention;

[0009]FIG. 2 illustrates an IC comprising devices to implement burn-intesting and binning, in accordance with one embodiment of the invention;

[0010]FIG. 3 is a simplified view of several electronic componentsmounted on a burn-in test fixture, in accordance with one embodiment ofthe invention;

[0011]FIG. 4 is a simplified view of burn-in test fixtures in a burn-inoven, in accordance with one embodiment of the invention; and

[0012]FIGS. 5A and 5B together illustrate a flow diagram of an improvedmethod of testing an IC comprising a plurality of electronic devices, inaccordance with one embodiment of the invention;

[0013]FIGS. 6A and 6B together illustrate a flow diagram of an improvedmethod of testing a plurality of electronic components, such as ICs, inaccordance with one embodiment of the invention; and

[0014]FIGS. 7A and 7B together illustrate a flow diagram of a method ofinstructing a processor to perform a method of binning a plurality ofICs, wherein each IC has a thermal sense circuit and a uniqueidentifier, in accordance with one embodiment of the invention

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0015] In the following detailed description of embodiments of theinvention, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, procedural,mechanical, and electrical changes may be made without departing fromthe spirit and scope of the present inventions. The following detaileddescription is, therefore, not to be taken in a limiting sense, and thescope of the present invention is defined only by the appended claims.

[0016] The present invention provides improved methods for performingburn-in testing of electronic components, such as ICs. By comparing atemperature indication provided by an on-board thermal sense circuitlocated on each IC with a gradually decrementing temperature value, allof the ICs can be characterized or binned according to a desired thermalparameter, such as junction temperature. Bin split can be improved byadjusting the burn-in conditions to limit yield loss that results fromthermal run-away. Further, a real-time estimate of the burn-in time foreach IC is obtained, so that burn-in time can be adjusted in real-timeto maximize burn-in throughput. Various embodiments are illustrated anddescribed herein, including methods of testing and binning, as well asan IC having an interface circuit to a burn-in system, an IC burn-insystem, and a computer-readable medium comprising computer instructionsfor instructing a processor to perform a method of binning a pluralityof ICs each having a thermal sense circuit.

[0017]FIG. 1 illustrates a block diagram of a burn-in system 1 toperform component burn-in testing and binning, in accordance with oneembodiment of the invention. Burn-in system 1 is merely one example of aburn-in system in which the present invention can be used. In thisexample, burn-in system 1 is implemented with a data processing system.

[0018] Burn-in system 1 includes equipment such as a burn-in receptacleor fixture 4 (shown in greater detail in FIG. 3). In one embodiment,fixture 4 contains a plurality of printed circuit boards (PCBs), each ofwhich in turn includes a plurality of ICs undergoing burn-in test;however, in other embodiments, fixture 4 could contain other types ofelectronic components, examples of which are described elsewhere herein.

[0019] Burn-in system 1 comprises at least one processor 6. As usedherein, “processor” means any type of computational circuit, such as butnot limited to a microprocessor, a microcontroller, a complexinstruction set computing (CISC) microprocessor, a reduced instructionset computing (RISC) microprocessor, a very long instruction word (VLIW)microprocessor, an application-specific integrated circuit (ASIC), anartificial intelligence circuit, neural network, or any other type ofcircuit for performing processing functions, or a combination of suchcomputational circuits.

[0020] Burn-in system 1 includes a system bus 2 to providecommunications links among the various components of burn-in system 1.System bus 2 can be implemented as a single bus, as a combination ofbusses, or in any other suitable manner.

[0021] Burn-in system 1 can also include an external memory 10, which inturn can include one or more memory or storage elements, such as a mainmemory 12 in the form of random access memory (RAM), one or more harddrives 14, and/or one or more drives that handle removable media 16 suchas floppy diskettes, compact disks (CDs), tape drives, and the like.

[0022] Burn-in system 1 can also include a display device 8 and akeyboard and/or controller 20, which can include a mouse, trackball,voice-recognition device, or any other device that permits a system userto input information into and receive information from burn-in system 1.

[0023] In operation, processor 6 of burn-in system 1 controls burn-inand/or binning functions under the direction of computer instructions.The computer instructions are stored on one or more computer-readablemedia within burn-in system 1, including any or all of the memoryelements within external memory 10, and/or within memory elements suchas high-speed cache (not shown) of processor 6.

[0024]FIG. 2 illustrates an IC 100 comprising devices to implementburn-in testing and binning, in accordance with one embodiment of theinvention. IC 100 is only one example of an IC that can be tested and/orbinned using the present invention.

[0025] In the embodiment illustrated in FIG. 2, IC 100 comprises aprocessor 102, which can be any type of computational circuit such as,but not limited to, those listed earlier. Processor 102 is coupled tobi-directional internal bus 120.

[0026] However, the present invention should not be construed as limitedto the burn-in and binning of processor ICs, because it can also beapplied to any other type of IC, such as memory chips, chipsetcomponents, peripheral component interconnect (PCI) devices, buscontrollers, high-volume data exchange devices, amplifiers, thyristors,or the like. Any type of IC having an on-board thermal sense circuit canbe tested and/or binned using the present invention.

[0027] IC 100, in this embodiment, also comprises a memory circuit ormemory 104 coupled to internal bus 120. Memory 104 can be of any type orsize, provided only that it has sufficient storage space to store atemperature value. In an alternative embodiment, memory 104 can beeliminated from IC 100, and a temperature value is stored in a memorycircuit or memory segment of burn-in system 1 (FIG. 1).

[0028] IC 100, in this embodiment, also comprises logic circuitry 106coupled to internal bus 120. Logic circuitry 106 can be of any type,provided only that it can perform a comparison function ormatch-determining function between a temperature indication generated bythermal sense circuitry 108 and a temperature value stored in memory,either in memory 104 or in burn-in system 1 (e.g. in external memory 10,FIG. 1). In an alternative embodiment, logic circuitry 106 can beeliminated from IC 100, and a match-determining function is performed byprocessor 6 (FIG. 1) of burn-in system 1.

[0029] IC 100 additionally comprises thermal sense circuitry 108 coupledto internal bus 120. Thermal sense circuitry 108 can be implemented byany circuit that is capable of generating a temperature parameter ortemperature indication. In one embodiment, thermal sense circuitry 108provides an indication proportional to or indicative of the substratetemperature or junction temperature on IC 100. Thermal sense circuit 108can be implemented, for example, by a temperature-sensing diode such asa forward-biased diode.

[0030] IC 100 also comprises suitable interface circuitry 110 betweeninternal bus 120 and test fixture bus 112, to transmit data,instructions, and/or control signals between IC 100 and burn-in system 1(FIG. 1).

[0031]FIG. 3 is a simplified view of several electronic components 100mounted on a burn-in test fixture 150, in accordance with one embodimentof the invention. Test board or test fixture 150 comprises a pluralityof sockets or connectors (not shown) to which one or more electroniccomponents 100 are coupled. In one embodiment, electronic components 100are ICs; however, in other embodiments electronic components can bevirtually any other type of electronic or electrical device thatgenerates heat in operation. Examples include cellular phones, pagers,computers of all types, electric tools, appliances, entertainmentequipment, aerospace and vehicular components, and the like.

[0032] Test fixture 150 comprises a bus 112 (FIG. 2) to which electroniccomponents 100 are electrically connected to burn-in system 1 (FIG. 1).

[0033]FIG. 4 is a simplified view of test fixtures 150 in a burn-in oven200, in accordance with one embodiment of the invention. Burn-in testfixtures 150 are situated within an environmentally controlled chambercontaining a temperature-altering mechanism, such as a heater and/or achiller. In one embodiment, the chamber is heated; however, in anotherembodiment, the chamber could be chilled. Burn-in system 1, operatingunder the control of a human operator or of computer instructions,thermally stresses the electronic components 100 on test fixtures 150by, for example, elevating the temperature in burn-in oven 200.

[0034] In an embodiment wherein the electronic components 100 beingburned-in are ICs, in addition to being heat-stressed they are typicallysubjected to higher operating voltages. The burn-in voltage variesaccording to the type of IC and the process used to fabricate it. Forexample, a burn-in voltage of 2.1 volts is used for one currentprocessor IC product. In addition to increasing the operating voltage,it is desirable to toggle most if not all of the circuit nodes withinthe ICs during the burn-in period

[0035] Thus, while burn-in test fixtures 150 are inside burn-in oven200, they are functionally connected to burn-in system 1 (FIG. 1) via anetwork of connectors and wires (not shown) in order to operate the ICson test fixtures 150 at elevated operating voltage and to toggle as manycircuit nodes as possible on the ICs. Burn-in oven 200 can also includepower and clock circuits (not shown) to provide power and clock signalsto the ICs undergoing burn-in.

[0036]FIGS. 5A and 5B together illustrate a flow diagram of an improvedmethod 500 of testing an IC comprising a plurality of circuits orelectronic devices, in accordance with one embodiment of the invention.A first one of the electronic devices provides a temperature indication,and this device can be any suitable thermal sense device, such asthermal sense circuitry 108 (FIG. 2). An optional, second one of theelectronic devices stores a temperature value, and this device can beimplemented by any suitable memory storage device, such as memorycircuit 104 (FIG. 2). If the optional, second memory storage device isnot on the IC, the memory storage function can be performed by suitablememory storage within burn-in system 1 (FIG. 1).

[0037] In 502, a temperature value is stored for the IC, either in thesecond electronic device or in a burn-in system coupled to the IC. Atemperature value above the highest expected junction temperature of theIC is chosen. For example, in one burn-in embodiment, a temperaturevalue of approximately 110 degrees C. is initially stored.

[0038] In 504, the IC is thermally stressed by elevating or lowering itsambient temperature. For burning-in ICs, the temperature is raised, e.g.to 60 degrees C.

[0039] In 506, the first electronic device (e.g. a temperature sensingdiode) provides a temperature indication.

[0040] In 508, a determination is made whether the temperatureindication matches the stored temperature value. “Match” means havingthe same value or substantially the same value. If there is a match, themethod goes to 510; otherwise, it goes to 512.

[0041] In 510, the temperature value is recorded, and the process endsfor this IC.

[0042] In 512, the temperature value is incremented to a new temperaturevalue, by lowering it one or two degrees (e.g. for a burn-in test), orby raising it one or two degrees (e.g. for a cold test).

[0043] In 514, a determination is made whether the temperatureindication matches the new stored temperature value. If so, the methodgoes to 516; other wise, it returns to 512.

[0044] In 516, the temperature value is recorded.

[0045] In 518, the process ends for this IC.

[0046]FIGS. 6A and 6B together illustrate a flow diagram of an improvedmethod 600 of testing a plurality of electronic components, such as ICs,in accordance with one embodiment of the invention. Electroniccomponents could also be any other type of component besides an IC,examples of which are provided elsewhere in this description. Eachelectronic component comprises a thermal sense circuit. Each electroniccomponent can also comprise an optional, storage circuit. If theelectronic component doesn't have the optional, storage circuit, thememory storage function can be performed by suitable memory storagewithin burn-in system 1 (FIG. 1). Each electronic component is alsoidentified by a unique identification (ID), which can be of any type butis typically a number.

[0047] In 602, a temperature value is stored for each component, eitherin the component's optional storage circuit or in a burn-in systemcoupled to the component.

[0048] In 604, the components are thermally stressed, e.g. by elevatingthe ambient temperature.

[0049] In 606, the thermal sense units each provide a temperatureindication for their respective components.

[0050] In 608, a determination is made whether the temperatureindication for each of the plurality of electronic components matchesthe temperature value. For those components for which this is true, theprocess goes to 610; otherwise, it goes to 612, for those components forwhich this is not true.

[0051] In 610, the temperature value and unique ID are recorded for eachelectronic component whose temperature indication matched thetemperature value in 608. From 610, the process goes to 618.

[0052] In 612, the temperature value is changed to a new temperaturevalue (e.g. a lower temperature value for a burn-in operation).

[0053] In 614, a determination is made whether the temperatureindication for each of the plurality of electronic components stillbeing evaluated at this point matches the temperature value. If so, theprocess goes to 616 for those components for which the match is true;otherwise, it returns to 612 for those components for which the match isfalse.

[0054] In 616, the temperature value and unique ID are recorded for eachelectronic component whose temperature indication matched thetemperature value in 616. From 616, the process goes to 618.

[0055] In 618, a determination is made whether all electronic componentshave had a temperature value recorded for them. If so, the process goesto 620 and ends; otherwise, it returns to 612.

[0056] In the present invention, the stimulus pattern for the componentsbeing tested during burn-in can be the same for all components undertest. It is unnecessary to provide a unique test stimulus pattern toeach component undergoing the burn-in test.

[0057]FIGS. 7A and 7B together illustrate a flow diagram of a method 700of instructing a processor to perform a method of binning a plurality ofICs, wherein each IC has a thermal sense circuit and a unique identifier(ID), in accordance with one embodiment of the invention. The processoris an element in a system that includes a temperature-altering mechanismto thermally stress the ICs. In a burn-in system, thetemperature-altering mechanism raises the ambient temperature; in achill-down system, the temperature-altering mechanism lowers the ambienttemperature. The system also includes a comparison mechanism that can beimplemented in any suitable manner, e.g. using a “compare” programinstruction or a hard-wired comparison circuit.

[0058] In 702, a temperature value is stored for the ICs undergoingtest. For an IC burn-in operation, a temperature value above the highestexpected junction temperature of any of the ICs is chosen. For example,in one burn-in embodiment, a temperature value of approximately 110degrees C. is initially stored.

[0059] In 704, a temperature indication is obtained from the thermalsense circuit of each IC. Each temperature indication is suitably linkedwith the IC generating it. This can be done, for example, using the IC'sID, and storing an ID/temperature indication pair for each IC under testat this point.

[0060] In 706, for each IC, the stored temperature value is comparedwith its own temperature indication.

[0061] In 708, a determination is made, for each IC, whether itstemperature indication substantially matches the stored temperaturevalue. If so, the process goes to 710; otherwise, it goes to 712.

[0062] In 710, for each IC for which the match of 708 is true, thetemperature value and unique ID are recorded. Also, at this time, usingthe temperature value recorded for the ICs for which the match of 708 istrue, an estimate of the burn-in time can be calculated if desired. Thisestimate can be further refined as additional ICs are binned in 712 and714, and in successive iterations of 712 and 714. From 710, the processgoes to 718.

[0063] In 712, the temperature value is changed to a new temperaturevalue (e.g. a lower temperature value for a burn-in operation).

[0064] In 714, a determination is made, for each IC, whether itstemperature indication substantially matches the new stored temperaturevalue. If so, the process goes to 716; otherwise, it returns to 712.

[0065] In 716, for each IC for which the match of 714 is true, thetemperature value and unique ID are recorded.

[0066] In 718, a check is made whether all ICs have had a temperaturevalue and ID recorded for them. If so, the process goes to 720; else, itreturns to 712.

[0067] In 720, the process ends.

[0068] The operations described above with respect to the methodsillustrated in FIGS. 5, 6A, 6B, 7A, and 7B can be performed in adifferent order from those described herein.

Determining Junction Temperature Tj for Each Component

[0069] The present invention can determine a junction temperature Tj foreach IC undergoing a burn-in test. Making use of a temperatureindication generated by thermal sense device on-board each IC, theburn-in system initially stores a temperature value above the highestexpected junction temperature Tj for the group of ICs undergoing test.By successively comparing the temperature indication output by thethermal sense device of each IC and decrementing the temperature valuein successive steps of a degree or two, eventually a match,corresponding to the junction temperature Tj, will be made and recordedfor each IC in the group of ICs.

[0070] The junction temperature Tj of an IC can be represented byEquation (1) as follows:

T _(j) =T _(a)+(θ_(ja) ×P _(d))   Equation (1)

[0071] wherein T_(j)= junction temperature (in degrees C.);

[0072] T_(a)=ambient temperature (in degrees C.);

[0073] θ_(ja)=the junction-to-ambient thermal resistance (in degreesC./watt), which can be in the range of 0.4-2.0 C./watt for some currentprocessor products; and

[0074] P_(d)=power dissipation at T_(j) (in watts), which can be in therange of 10-60 watts for some current processors products.

[0075] By obtaining a distribution of junction temps for all ICsundergoing burn-in testing, the present invention provides a directassessment of the burn-in test stability. It also allows an ICmanufacturer to substantially remove any thermal margin from burn-intesting by allowing parts having a shorter channel length, and/or partsoperating at a higher power or frequency into burn-in testing. It alsoincreases overall bin split, as will now be discussed immediately below.

Increasing Bin Split

[0076] The present invention provides a relatively high bin split forelectronic components undergoing thermal stress testing. “Bin split” isthe process of evaluating a group of electronic components, such as ICs,to sort or allocate them into a number of different groups according tosome characteristic. The characteristic could be, for example, aperformance-related characteristic or an operational-relatedcharacteristic, such as standby current I_(SB). High performanceprocessors generally operate at a higher I_(SB) value (and acorrespondingly higher junction temperature Tj) compared with lowerperformance processors of the same design running at the same clockspeed.

[0077] In general, the higher the junction temperature Tj, the shorterthe burn-in time BITM. However, if the burn-in conditions are set toohigh, the risk of thermal run-away increases. By obtaining a Tj for eachcomponent, the burn-in conditions can be set to maximize bin split andto limit yield loss that results from thermal run-away.

[0078] In this invention, distribution of junction temps between thelowest performance processor and highest performance processor of abatch undergoing burn-in testing can be determined at a relatively fineincrement, such as degree-by-degree from 110 degrees C. down to 60degrees C. By obtaining a Tj value for each component, thermal margin isbetter understood, and transistor channel length L_(E) can be retargeted(e.g. shortened) to obtain higher frequency bin split.

[0079] How the present invention provides for a relatively high binsplit will now be discussed.

[0080] Each IC has an on-chip thermal sense circuit that provides T_(j)for the IC. Ambient temperature T_(a) is maintained constant in theburn-in oven, e.g. at 60 C. Burn-in voltage V_(BI) is maintainedconstant during burn-in, e.g. V_(BI)=2.1 volts for one current processorproduct having a normal operating voltage of 1.7 volts.

[0081] An initial temperature value (e.g. 110 C.) is programmed for allICs, and all ICs are checked to see whether any have a junctiontemperature indication T_(j) of 110 C. Any ICs whose T_(j) is 110 C. areidentified. For each of these ICs, the ID and the 110 C. value arestored.

[0082] Next the temperature value is decremented to 109 C., and all ICsare again checked. Any ICs whose T_(j) is 109 C. are identified.

[0083] This is continued down to a relatively low temperature, e.g. 60C., and/or until a T_(j) value has been logged for all ICs (exceptingthose that may have failed during burn-in testing). This continuousmonitoring of Tj allows the burn-in conditions to be adjusted tominimize yield loss due to thermal run-away, and thus to improve binsplit.

[0084] The ICs are binned according to their T_(j) values. Those withthe highest T_(j) values are generally capable of highest performance.

Determining Burn-In Time (BITM)

[0085] Burn-in testing to screen out infant-mortality failures bytesting at elevated voltages and temps is performed for a specifiedlength of time, referred to as the burn-in time BITM. BITM must be longenough in duration to provide satisfactory statistical and experientialassurance that most, if not all, of the failure-prone electroniccomponents under test will have been identified. However, there is apractical upper limit to BITM duration, which is driven in part by highvolume manufacturing costs (including labor costs and energy costs), byproduction throughput requirements, and by a potential decrease inproduct reliability in that the stresses applied during burn-in mayadversely impact reliability once components are installed in customers'products.

[0086] The present invention can achieve significant savings in theburn-in test process by accurately determining the BITM for eachcomponent undergoing burn-in testing in the test fixture, as will now beexplained.

[0087] BITM can be calculated from Equation (2):

BITM=A _(v) *A _(T)   Equation (2)

[0088] wherein A_(v) is a voltage acceleration factor. For one currentprocessor product, A_(v) is approximately 30.

[0089] A_(T) is a temperature acceleration factor that can vary withinICs of the same design. A_(T) is derivable from the well-known Arrheniusrelationship expressed in Equation (3):

A _(T)=exp [(Ea/k) (1/T1−1/T2)]  Equation (3)

[0090] wherein Ea is an activation energy (in eV), typically in therange of 0.3-2.0 eV;

[0091] k is Bolzmann's constant=8.617×10⁻⁵ eV/K;

[0092] T₁ is the intended use temperature for the IC (in degrees C.);and

[0093] T₂ is the burn-in temperature (in degrees C.).

[0094] A_(T) is a function of power P_(d) dissipated from the IC, and itcan vary within ICs of the same design. P_(d) is a function of standbycurrent I_(SB) to the IC, and it can vary within ICs of the same design.I_(SB) is a function of transistor channel length L_(E) and otherprocess parameters, and it can vary within ICs of the same design.

[0095] Using the binning operation performed earlier, A_(T) can beobtained for each IC, so BITM can be readily calculated in real time foreach individual IC undergoing burn-in, using Equation (2) above.

[0096] As a result, the BITM can be dynamically varied. For example,BITM can be shortened or lengthened to correspond with the highestcalculated BITM for any IC undergoing burn-in.

[0097] Alternatively, BITM can be kept relatively constant, but certaintest fixtures could be pulled from the burn-in oven early if all oftheir ICs have completed burn-in, and other test fixtures could be leftin the burn-in oven longer, if some of their ICs require a longer thannormal burn-in time.

[0098] Thus, the burn-in test process can result in significant savingsin labor, energy, and production time. It can also result in asignificant increase in quality over a burn-in process that uses only astatic BITM.

Conclusion

[0099] The present invention provides improved methods for performingburn-in testing and/or binning of electronic components, such as ICs. Bycomparing a temperature indication provided by an on-board thermal sensecircuit of each IC with a gradually decrementing thermal set-pointvalue, all of the ICs can be characterized or binned according to adesired thermal parameter, such as junction temperature. By employingthe burn-in testing concepts of the present invention, it is unnecessaryto provide a unique test stimulus pattern to each component under test.The stimulus pattern can be the same for all components undergoing theburn-in test.

[0100] A relatively high bin split is obtained, because burn-inconditions can be tuned to minimize thermal run-away loss. In addition,thermal margin based upon Tj can be removed to improve BITM, e.g. byincreasing the ambient temperature T_(a). Further, a real-time estimateof the burn-in time for each IC is obtained, so that burn-in time can beadjusted to optimize burn-in throughput, and to reduce production costs.

[0101] In addition to the above-mentioned methods, an IC having aninterface circuit to a burn-in system, an IC burn-in system, and acomputer-readable medium comprising computer instructions forinstructing a processor to perform a method of binning a plurality ofICs have been described.

[0102] As shown herein, the present invention can be implemented in anumber of different embodiments. Other embodiments will be readilyapparent to those of ordinary skill in the art. The elements,architecture, functions, and sequence of operations can all be varied tosuit particular product and test requirements.

[0103] For example, instead of recording the temperature value when amatch occurs, the temperature indication could be recorded, because itis either identical to or substantially identical to the temperaturevalue. Also, the components undergoing burn-in testing could besubjected to other environmental accelerators, such as humidity,vibration, thermal cycling, and so forth.

[0104] Also, instead of storing a temperature value (e.g. initially ahigh value), comparing a temperature indication generated by a thermalsense unit on each IC with the temperature value, logging any matches,and then successively decrementing the temperature value until a Tjvalue has been recorded for all ICs, a slightly different implementationcould be used in which a thermal set-point is loaded into each IC. Whilethe ICs are maintained at a constant elevated temperature, the burn-insystem checks each IC to determine whether the set-point has beenexceeded. If so, it characterizes the component by that set-point; ifnot, it decrements the set-point and checks again. This process wouldcontinue until all ICs have been characterized to a specific set-point.As a result of the method, a junction temperature is obtained for eachIC.

[0105] The various elements depicted in the drawings are merelyrepresentational and are not drawn to scale. Certain proportions thereofmay be exaggerated, while others may be minimized. The drawings areintended to illustrate various implementations of the invention, whichcan be understood and appropriately carried out by those of ordinaryskill in the art.

[0106] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

What is claimed is:
 1. An integrated circuit (IC) comprising: interfacecircuitry to interface the IC to a burn-in system, the interfacecircuitry to receive at least one temperature value from the burn-insystem and to send at least one temperature indication to the burn-insystem; a storage circuit coupled to the interface circuitry to storethe at least one temperature value; and a thermal sense circuit coupledto the interface circuitry to provide the at least one temperatureindication.
 2. The IC recited in claim 1, wherein the at least onetemperature value is a set-point.
 3. The IC recited in claim 1, whereinthe at least one temperature indication is proportional to the junctiontemperature of the IC.
 4. An integrated circuit (IC) bum-in systemcomprising: a computer system comprising a processor operating under thecontrol of a computer program; and at least one IC comprising: interfacecircuitry to interface the IC to the computer system; and a thermalsense circuit, coupled to the interface circuitry, to provide atemperature indication that is proportional to the junction temperatureof the IC.
 5. The IC burn-in system recited in claim 4, wherein thecomputer system compares the temperature indication with a temperaturevalue determined by the computer program; wherein if the temperatureindication substantially matches the temperature value, the computersystem bins the IC at that temperature value; and wherein if thetemperature indication is less than the temperature value, the computersystem decrements the temperature value and compares the temperatureindication with the decremented temperature value.
 6. The IC burn-insystem recited in claim 4, wherein the IC further comprises: logiccircuitry coupled to the interface circuitry; and wherein the logiccircuitry is responsive to the temperature indication generated by thethermal sense circuit; wherein the logic circuit is also responsive to atemperature value generated by the computer system as determined by thecomputer program; wherein the logic circuitry compares the temperatureindication with the temperature value; wherein if the temperatureindication substantially matches the temperature value, the logiccircuitry generates a first indication to the computer system, and thecomputer system bins the IC at that temperature value; and wherein ifthe temperature indication is less than the temperature value, the logiccircuitry generates a second indication to the computer system, and thecomputer system decrements the temperature value and compares thetemperature indication with the decremented temperature value.
 7. Aburn-in system for an IC comprising a thermal sense circuit, the burn-insystem comprising: a fixture to electrically couple to the IC; atemperature-altering mechanism to alter the ambient temperature of theIC; and a data processing system coupled to the fixture, the dataprocessing system executing a computer program, the computer programoperating the burn-in system to characterize the IC and comprising theoperations of: storing a temperature value for the IC; controlling thetemperature-altering mechanism to thermally stress the IC; determiningwhether a temperature indication from the thermal sense circuitsubstantially matches the temperature value; if so, recording thetemperature value; and if not, changing the temperature value to a newtemperature value and determining whether the temperature indicationmatches the new temperature value.
 8. The burn-in system recited inclaim 7, wherein the computer program operating the burn-in systemfurther comprises the operations of: determining whether the temperatureindication matches the new temperature value; if so, recording the newtemperature value; otherwise, repeatedly changing the temperature valueand comparing the temperature indication with the changed temperaturevalue, until the temperature indication matches the changed temperaturevalue; and recording the changed temperature value.
 9. The burn-insystem recited in claim 7, wherein the temperature value is stored in astorage circuit in the IC.
 10. The bum-in system recited in claim 7,wherein the temperature value is stored in a storage element in the dataprocessing system.
 11. A method of testing an integrated circuit (IC)comprising a plurality of electronic devices, one of which is to providea temperature indication, the method comprising: storing a temperaturevalue for the IC; thermally stressing the IC; the one electronic deviceproviding a temperature indication; determining whether the temperatureindication matches the temperature value; if so, recording thetemperature value; and if not, changing the temperature value to a newtemperature value and determining whether the temperature indicationmatches the new temperature value.
 12. The method recited in claim 11and further comprising; if the temperature indication matches the newtemperature value, recording the temperature value; otherwise,repeatedly changing the temperature value and comparing the temperatureindication with the changed temperature value, until the temperatureindication matches the changed temperature value; and recording thechanged temperature value.
 13. The method recited in claim 11, whereinstoring is performed by another one of the plurality of electronicdevices in the IC.
 14. The method recited in claim 11, wherein storingis performed by a burn-in system coupled to the IC and comprising astored-program digital computer.
 15. The method recited in claim 11,wherein the plurality of electronic devices includes a logic circuit,and wherein determining is performed by the logic circuit.
 16. Themethod recited in claim 11, wherein determining is performed by aburn-in system coupled to the IC and comprising a stored-program digitalcomputer.
 17. A method of testing a plurality of integrated circuits(ICs), each comprising a thermal sense circuit, the method comprising:storing a temperature value for each IC; thermally stressing the ICs;each thermal sense circuit providing a temperature indication for itsrespective IC; determining whether the temperature indication matchesthe temperature value; if so, recording the temperature value for thecorresponding IC; and if not, changing the temperature value to a newtemperature value and determining whether the temperature indicationmatches the new temperature value.
 18. The method recited in claim 17and further comprising; if the temperature indication matches the newtemperature value, recording the temperature value for the correspondingIC; otherwise, repeatedly changing the temperature value and comparingthe temperature indication with the changed temperature value, until thetemperature indication matches the changed temperature value; andrecording the changed temperature value for the respective IC.
 19. Themethod recited in claim 17, wherein each IC comprises a storage circuit,and wherein storing is performed by the storage circuit.
 20. The methodrecited in claim 17, wherein storing is performed by a burn-in systemcoupled to the IC and comprising a stored-program digital computer. 21.The method recited in claim 17, wherein each IC comprises a logiccircuit, and wherein determining is performed by the logic circuit. 22.The method recited in claim 17, wherein determining is performed by aburn-in system coupled to the IC and comprising a stored-program digitalcomputer.
 23. A method of testing a plurality of electronic components,each comprising a thermal sense circuit, the method comprising: storinga temperature value for each electronic component; thermally stressingthe electronic components; each thermal sense circuit providing atemperature indication for its respective electronic component;determining whether the temperature indication matches the temperaturevalue; if so, recording the temperature value for the correspondingelectronic component; and if not, changing the temperature value to anew temperature value and determining whether the temperature indicationmatches the new temperature value.
 24. The method recited in claim 23and further comprising; if the temperature indication matches the newtemperature value, recording the temperature value for the correspondingelectronic component; otherwise, repeatedly changing the temperaturevalue and comparing the temperature indication with the changedtemperature value, until the temperature indication matches the changedtemperature value; and recording the changed temperature value for therespective electronic component.
 25. The method recited in claim 23,wherein each electronic component comprises a storage circuit, andwherein storing is performed by the storage circuit.
 26. The methodrecited in claim 23, wherein storing is performed by a burn-in systemcoupled to the electronic component and comprising a stored-programdigital computer.
 27. The method recited in claim 23, wherein eachelectronic component comprises a logic circuit, and wherein determiningis performed by the logic circuit.
 28. The method recited in claim 23,wherein determining is performed by a burn-in system coupled to theelectronic component and comprising a stored-program digital computer.29. The method recited in claim 23, wherein the electronic componentsare integrated circuits.
 30. A computer-readable medium containingcomputer instructions for instructing a processor to perform a method ofbinning a plurality of ICs each having a thermal sense circuit, theprocessor forming an element in a system comprising atemperature-altering mechanism to thermally stress the ICs and acomparison mechanism, wherein the instructions comprise: storing atemperature value for each IC; obtaining a temperature indication fromthe thermal sense circuit of each IC; for each IC not yet binned,comparing the stored temperature value with the temperature indication;and if the temperature indication substantially matches the storedtemperature value, recording the temperature value; otherwise, changingthe temperature value to a new temperature value and comparing the newtemperature value with the temperature indication.
 31. Thecomputer-readable medium recited in claim 30, wherein the instructionsfurther comprise: if the temperature indication substantially matchesthe new temperature value, recording the new temperature value;otherwise, repeatedly changing the temperature value and comparing thetemperature indication with the changed temperature value, until thetemperature indication substantially matches the changed temperaturevalue, and recording the changed temperature value.
 32. Thecomputer-readable medium recited in claim 30, wherein the instructionsfurther comprise: determining an estimate of the bum-in time for eachIC, using the particular temperature value recorded for each IC.